The present disclosure relates generally to forming an integrated circuit device on a substrate and, more particularly, to forming a gate oxide layer of a semiconductor device.
Semiconductor device geometries continue to dramatically decrease in size. Today's fabrication processes are routinely producing devices having feature dimensions less than 65 nm. However, solving the problems associated with implementing new process and equipment technology while continuing to satisfy device requirements has become more challenging. For example, metal-oxide-semiconductor (MOS) transistors have typically been formed with polysilicon gate electrodes. Polysilicon has advantageous thermal resistive properties and can allow for formation of self aligned source/drain structures.
However, in order to continually meet performance requirements, has been a desire to replace the polysilicon gate electrode with a metal gate electrode. One process of implementing metal gates is terms a “gate last” or “replacement gate” methodology. In such a process, a dummy (e.g., sacrificial) polysilicon gate is initially formed, various processes associated with the semiconductor device are performed, and the dummy gate is subsequently removed and replaced with a metal gate. However, problems arise when integrating a gate last process with other fabrication processes such as the formation of multiple gate oxide configurations on the same device (e.g., chip or die) such as in system-on-a-chip (SOC) designs.